Currently, integrated circuit (IC) package assemblies may include package-on-package (PoP) configurations where a first package substrate is coupled with a second package substrate using an interposer disposed between the first and second package substrate. For example, the first package substrate may be a thin coreless substrate for a processor and the second package substrate may be for a memory component and the first and second package substrate may each be coupled with the interposer using micro solder balls. A resulting PoP structure using the interposer may have a height (e.g., z-height) that limits implementation of the PoP structure in small form factor devices such as, for example, mobile computing devices that continue to shrink to smaller dimensions.
Furthermore, the thin coreless substrate may require a fixture jig to handle the substrate during assembly processes such as solder ball reflow, die attach, and/or interposer attach operations owing to lack of structural rigidity. Using the fixture jig may increase assembly costs and complexity. Additionally, in some cases, a high temperature (e.g., ˜260° C.) thermal process may be used to couple the die with the substrate using a solderable material, which may result in thermal stress related defects (e.g., warpage) due to difference in coefficient of thermal expansion (CTE) between the die and the substrate.